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features ? single supply for read and write: 2.7v to 5.5v ? fast read access time ? 70 ns (v cc = 2.7v to 3.6v); 55 ns (v cc = 4.5v to 5.5v) ? internal program control and timer ? flexible sector architecture ? one 16k bytes boot sector with programming lockout ? two 8k bytes parameter sectors ? eight main memory sectors (one 32k bytes, seven 64k bytes) ? fast erase cycle tim e ? 8 seconds ? byte-by-byte programming ? 10 s/byte typical ? hardware data protection ? d a t a polling or toggle bit for end of program detection ? low power dissipation ? 20 ma active current ? 25 a cmos standby current for v cc = 2.7v to 3.6v ? 30 a cmos standby current for v cc = 4.5v to 5.5v ? minimum 100,000 write cycles 1. description the at49bv040b is a 2.7v to 5.5v in-system reprogrammable flash memory. its 4 megabits of memory is organized as 524,288 words by 8 bits. manufactured with atmel?s advanced nonvolatile cmos technology, the device offers an access time of 70 ns (v cc = 2.7v to 3.6v) and an access time of 55 ns (v cc = 4.5v to 5.5v). the power dissipation over the industrial temperature range with v cc = 2.7v to 3.6v is 72 mw and is 110 mw with v cc = 4.5v to 5.5v. when the device is deselected, the cmos standby current is less than 30 a. to allow for simple in-system reprogrammability, the at49bv040b does not require high input voltages for programming. reading data out of the device is similar to reading from an eprom; it has standard c e, o e, and w e inputs to avoid bus contention. reprogramming the at49bv040b is performed by erasing a sector of data and then programming on a byte by byte basis. the byte programming time is a fast 10 s. the end of a program or erase cycle can be optionally detected by the d a t a polling or toggle bit feature. once the end of a byte program cycle has been detected, a new access for a read or program can begin. the typical number of program and erase cycles is in excess of 100,000 cycles. the device is erased by executing a chip erase or a sector erase command sequence; the device internally controls the erase operations. the memory array of the at49bv040b is organized into two 8k byte parameter sectors, eight main memory sectors, and one boot sector. the device has the capability to protect the data in the boot sector; this feature is enabled by a command sequence. the 16k-byte boot sector includes a reprogram- ming lock out feature to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. 4-megabit (512k x 8) flash memory at49bv040b not recommended for new design 3499b?flash?4/06
2 3499b?flash?4/06 at49bv040b 2. pin configurations 2.1 32-lead plcc top view 2.2 32-lead vsop or 32-lead tsop top view ? type 1 pin name function a0 - a18 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 a16 a18 vcc we a17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3
3 3499b?flash?4/06 at49bv040b 3. block diagram 4. device operation 4.1 read the at49bv040b is accessed like an eprom. when c eand o e are low and w e is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line con- trol gives designers flexibility in preventing bus contention. 4.2 command sequences when the device is first powered on, it will be reset to the read or standby mode depending upon the state of the control line inputs. in order to perform other device functions, a series of com- mand sequences are entered into the device. the command sequences are shown in the command definitions table. the command sequences are written by applying a low pulse on the w eor c e input with c eor w e low (respectively) and o e high. the address is latched on the falling edge of c eor w e, whichever occurs last. the data is latched by the first rising edge of c eor w e. standard microprocessor write timings are used. the address locations used in the command sequences are not affected by entering the command sequences. control logic y decoder parameter sector 1 (8k bytes) boot sector (16k bytes) oe we ce address inputs vcc gnd data inputs/outputs i/o7 - i/o0 8 x decoder parameter sector 2 (8k bytes) main memory sector 1 (32k bytes) main memory sector 2 (64k bytes) main memory sector 3 (64k bytes) main memory sector 4 (64k bytes) main memory sector 8 (64k bytes) main memory sector 7 (64k bytes) main memory sector 6 (64k bytes) main memory sector 5 (64k bytes) program data latches y-gating input/output buffers 1ffff 10000 0ffff 08000 3ffff 30000 2ffff 20000 07fff 06000 05fff 04000 03fff 00000 7ffff 70000 6ffff 60000 5ffff 50000 4ffff 40000
4 3499b?flash?4/06 at49bv040b 4.3 erasure before a byte can be reprogrammed, it must be erased. the erased state of memory bits is a logical ?1?. the entire device can be erased by using the chip erase command or individual sec- tors can be erased by using the sector erase command. 4.3.1 chip erase if the boot block lockout has been enabled, the chip erase function will erase parameter sector 1, parameter sector 2, main memory sectors 1 - 8, but not the boot sector. if the boot sector lockout has not been enabled, the chip erase function will erase the entire chip. after the full chip erase the device will return back to read mode. any command during chip erase will be ignored. 4.3.2 sector erase as an alternative to a full chip erase, the device is organized into sectors that can be individually erased. there are two 8k-byte parameter sectors and eight main memory sectors. the 8k-byte parameter sectors and the eight main memory sectors can be independently erased and repro- grammed. the sector erase command is a six bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched at the rising edge of we. the sector erase starts after the rising edge of we of the sixth cycle. the erase operation is internally controlled; it will automatically time to completion. 4.4 byte programming once the memory array is erased, the device is programmed (to a logical ?0?) on a byte-by-byte basis. please note that a data ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. programming is accomplished via the internal device command register and is a 4-bus cycle operation (see ?command definition table? on page 7 ). the device will automatically generate the required internal program pulses. the program cycle has addresses latched on the falling edge of w eor c e, whichever occurs last, and the data latched on the rising edge of we or ce, whichever occurs first. programming is completed after the specified t bp cycle time. the d a t a polling or toggle bit feature may also be used to indicate the end of a program cycle. 4.5 boot sector programming lockout the device has one designated sector that has a programming lockout feature. this feature pre- vents programming of data in the designated sector once the feature has been enabled. the size of the sector is 16k bytes. this sector, referred to as the boot sector, can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; the boot sector?s usage as a write protected region is optional to the user. the address range of the boot sector is 00000 to 03fff. once the feature is enabled, the data in the boot sector can no longer be erased or pro- grammed. data in the main memory and parameter sectors can still be changed through the regular programming method. to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. see ?command definition table? on page 7 .
5 3499b?flash?4/06 at49bv040b 4.5.1 boot sector lockout detection a software method is available to determine if programming of the boot sector is locked out. when the device is in the software product identification mode ( see software product identification entry/exit on page 15 ) a read from address location 00002h will show if programming the boot sector is locked out. if the data on i/o0 is low, the boot sector can be programmed; if the data on i/o0 is high, the program lockout feature has been activated and the sector cannot be pro- grammed. the software product identification code should be used to return to standard operation. 4.6 product identification the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. 4.7 data polling the at49bv040b features data polling to indicate the end of a program or erase cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all out- puts and the next cycle may begin. d a t a polling may begin at any time during the program cycle. during a chip or sector erase operation, an attempt to read the device will give a ?0? on i/o7. once the erase operation is completed, a ?1? will be read from i/o7. the data polling sta- tus bit must be used in conjunction with the erase/program status bit as shown in the algorithm in figure 4-1 on page 6 . 4.8 toggle bit in addition to data polling, the at49bv040b provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. the toggle bit status bit should be used in conjunction with the erase/program status bit shown in the algorithm in figure 4-2 on page 6 . 4.9 erase/program status bit the device offers a status bit on i/o5, which indicates whether the program or erase operation has exceeded a specified internal pulse count limit. if the status bit is a ?1?, the device is unable to verify that an erase or a byte program operation has been successfully performed. if a pro- gram (sector erase) command is issued to the boot sector and the boot sector programming lockout feature is enabled, the boot sector will not be programmed (erased), and the device will go into the read mode. once the erase/program status bit has been set to a ?1?, the system must write the product id exit command to return to the read mode. the erase/program status bit is a ?0? while the erase or program operation is still in progress. 4.10 hardware data protection hardware features protect against inadvertent programs to the at49bv040b in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) program inhibit: holding any one of o e low, c e high or w e high inhibits program cycles. (c) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle.
6 3499b?flash?4/06 at49bv040b figure 4-1. data polling algorithm figure 4-2. toggle bit algorithm notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. i/o7 should be rechecked even if i/o5 = ?1? because i/o7 may change simultaneously with i/o5. note: 1. the system should recheck the toggle bit even if i/o5 = ?1? because the toggle bit may stop toggling as i/o5 changes to ?1?. start read i/o7 - i/o0 addr = va i/o7 = data? i/o5 = 1? read i/o7 - i/o0 addr = va i/o7 = data? program/erase operation not successful, write product id exit command no no no yes yes yes program/erase operation successful, device in read mode start read i/o7 - i/o0 read i/o7 - i/o0 toggle bit = to g g l e ? i/o5 = 1? read i/o7 - i/o0 tw i c e toggle bit = to g g l e ? program/erase operation not successful, write product id exit command program/erase operation successful, device in read mode no no no yes yes yes
7 3499b?flash?4/06 at49bv040b notes: 1. the data format in each bus cycle is as follows: i/o7 - i/o0 (hex). the address format in each bus cycle is as follows: a11 - a0 (hex); a11 - a18 (don?t care). 2. since a11 is don?t care, aaa can be replaced with 2aa. 3. the 16k byte boot sector has the address range 00000h to 03fffh. 4. either one of the product id exit commands can be used. 5. sa = sector addresses: sa = 00000 to 03fff for boot sector sa = 04000 to 05fff for parameter sector 1 sa = 06000 to 07fff for parameter sector 2 sa = 08000 to ffff for main memory array sector 1 sa = 10000 to 1ffff for main memory array sector 2 sa = 20000 to 2ffff for main memory array sector 3 sa = 30000 to 3ffff for main memory array sector 4 sa = 40000 to 4ffff for main memory array sector 5 sa = 50000 to 5ffff for main memory array sector 6 sa = 60000 to 6ffff for main memory array sector 7 sa = 70000 to 7ffff for main memory array sector 8 5. command definition table command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 555 aa aaa (2) 55 555 80 555 aa aaa 55 555 10 sector erase 6 555 aa aaa 55 555 80 555 aa aaa 55 sa (5) 30 byte program 4 555 aa aaa 55 555 a0 addr d in boot sector lockout (3) 6 555 aa aaa 55 555 80 555 aa aaa 55 555 40 product id entry 3 555 aa aaa 55 555 90 product id exit (4) 3 555 aa aaa 55 555 f0 product id exit (4) 1 xxx f0 6. absolute maximum ratings* temperature under bias ............................... -55c to +125c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions beyond those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on a9 with respect to ground ...................................-0.6v to +10.0v
8 3499b?flash?4/06 at49bv040b 7. sector address table sector sector size sector address range boot sector 16k bytes 00000 - 03fff parameter sector 1 8k bytes 04000 - 05fff parameter sector 2 8k bytes 06000 - 07fff main memory sector 1 32k bytes 08000 - 0ffff main memory sector 2 64k bytes 10000 - 1ffff main memory sector 3 64k bytes 20000 - 2ffff main memory sector 4 64k bytes 30000 - 3ffff main memory sector 5 64k bytes 40000 - 4ffff main memory sector 6 64k bytes 50000 - 5ffff main memory sector 7 64k bytes 60000 - 6ffff main memory sector 8 64k bytes 70000 - 7ffff
9 3499b?flash?4/06 at49bv040b notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 9.5v 0.5v. 4. manufacturer code: 1fh, device code: 13h. additional device code: 10h is read from address 0003h. 5. see details under software product identification entry/exit on page 15 . note: 1. in the erase mode, i cc is 15 ma. 8. dc and ac operating range at49bv040b operating temperature (case) ind. -40c - 85c v cc power supply 2.7v - 3.6v or 4.5v to 5.5v 9. operating modes mode ce oe we ai i/o read v il v il v ih ai d out program/erase (2) v il v ih v il ai d in standby/write inhibit v ih x (1) x x high z program inhibit x x v ih program inhibit x v il x output disable x v ih x high z product identification hardware v il v il v ih a1 - a18 = v il ,a9=v h , (3) ,a0=v il manufacturer code (4) a1 - a18 = v il ,a9=v h , (3) ,a0=v ih device code (4) software (5) a0 = v il ,a1-a18=v il manufacturer code (4) a0 = v ih ,a1-a18=v il device code (4) 10. dc characteristics symbol parameter condition v cc = 2.7v to 3.6v v cc = 4.5v to 5.5v units min typ max min typ max i li input load current v in =0vtov cc 11a i lo output leakage current v i/o =0vtov cc 11a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 15 25 25 30 a i cc (1) v cc active current f = 5 mhz; i out =0ma 15 20 15 20 ma v il input low voltage 0.1 v cc 0.1 v cc v v ih input high voltage 0.7 v cc 0.7 v cc v v ol output low voltage i ol = 2.1 ma 0.45 0.45 v v oh output high voltage i oh = -400 a 2.4 2.4 v
10 3499b?flash?4/06 at49bv040b 12. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc -t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce -t oe after the falling edge of ce without impact on t ce or by t acc -t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 11. ac read characteristics symbol parameter 2.7v to 3.6v 4.5v to 5.5v units min max min max t acc address to output delay 70 55 ns t ce (1) ce to output delay 70 55 ns t oe (2) oe to output delay 0 35 0 15 ns t df (3)(4) ce or oe to output float 0 25 0 25 ns t oh output hold from oe, ce or address, whichever occurred first 00 ns address output high z output oe ce t acc t oe t df t oh t ce valid address valid
11 3499b?flash?4/06 at49bv040b 13. input test waveform and measurement level t r ,t f <5ns 14. output load test note: 1. this parameter is characterized and is not 100% tested. ac measurement level ac driving levels 0.1xv cc 0.7xv cc v cc /2 output pin v cc 30 pf 1.8k 1.3k 15. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 4 6 pf v in =0v c out 812pfv out =0v
12 3499b?flash?4/06 at49bv040b 17. ac byte load waveforms 17.1 we controlled 17.2 ce controlled 16. ac byte load characteristics symbol parameter 2.7v to 3.6v 4.5v to 5.5v min max min max units t as ,t oes address, oe set-up time 0 0 ns t ah address hold time 20 20 ns t cs chip select set-up time 0 0 ns t ch chip select hold time 0 0 ns t wp write pulse width ( we or ce) 30 20 ns t ds data set-up time 20 20 ns t dh ,t oeh data, oe hold time 0 0 ns t wph write pulse width high 20 20 ns t dh t ds t as t ah t wp ce address data in oe t oes t oeh we t cs t ch t wph t dh t ds t as t ah t wp we address data in oe t oes t oeh ce t cs t ch t wph
13 3499b?flash?4/06 at49bv040b note: 1. 20 ns for v cc = 4.5v to 5.5v. 19. program cycle waveforms 20. sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 555. for sector erase the address depends on what sector is to be erased. (see note 5 under ?command definition table? on page 7 .) 3. for chip erase, the data should be 10h. for sector erase, the data should be 30h. 18. program cycle characteristics symbol parameter 2.7v to 3.6v and 4.5v to 5.5v units min typ max t bp byte programming time 10 120 s t as address set-up time 0 ns t ah address hold time 20 ns t ds data set-up time 20 ns t dh data hold time 0 ns t wp write pulse width 30 (1) ns t wph write pulse width high 20 ns t ec chip erase cycle time 8 seconds t sec main sector erase cycle time 900 ms a0-a1 8 oe (1) aa 80 note 3 55 55 555 555 note 2 aa byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 aaa aaa t wph t wp ce we a0 - a18 data t as t ah t ec t dh t ds 555
14 3499b?flash?4/06 at49bv040b notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. 22. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. 24. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 21. data polling characteristics symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns high z an an an an an we ce oe i/o7 a0-a18 t oeh t oe t dh t wr t oehp 23. toggle bit characteristics symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 50 ns t wr write recovery time 0 ns we ce oe i/o6 t oeh high z t dh t oe t wr t oehp
15 3499b?flash?4/06 at49bv040b 25. software product identification entry (1) 26. software product identification exit (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a11 - a0 (hex). 2. a1 - a18 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . additional device code is read for address 0003h 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 1fh device code: 13h. additional device code: 10h. load data aa to address 555 load data 55 to address aaa load data 90 to address 555 enter product identification mode (2)(3)(5) load data aa to address 555 load data 55 to address aaa load data f0 to address 555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) 27. boot block lockout feature enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a11 - a0 (hex). 2. boot block lockout feature enabled. load data aa to address 555 load data 55 to address aaa load data 80 to address 555 load data aa to address 555 load data 55 to address aaa load data 40 to address 555 pause 1 second (2)
16 3499b?flash?4/06 at49bv040b 28. ordering information 28.1 green package (pb/halide-free) i cc (ma) active ordering code package operation range 20 at49bv040b-ju at49bv040b-tu AT49BV040B-VU 32j 32t 32v industrial (-40 to 85 c) package type 32j 32-lead, plastic, j-leaded chip carrier package (plcc) 32t 32-lead, thin small outline package (tsop) 32v 32-lead, thin small outline package (vsop)
17 3499b?flash?4/06 at49bv040b 29. packaging information 29.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45 pin no. 1 identifier 1.14(0.045) x 45 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45 max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010 (0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004 (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
18 3499b?flash?4/06 at49bv040b 29.2 32t ? tsop 2325 orchard park w ay san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small o u tline package, type i (tsop) b 32t 10/18/01 pi n 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage pla n e seati n g pla n e l1 common dimensions (unit of meas u re = mm) symbol min nom max note n otes: 1. this package conforms to jedec reference mo-142, v ariation bd. 2. dimensions d1 and e do not incl u de mold protr u sion. allo w able protr u sion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maxim u m. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 n ote 2 e 7.90 8.00 8.10 n ote 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
19 3499b?flash?4/06 at49bv040b 29.3 32v ? vsop 2325 orchard park w ay san jose, ca 95131 title drawing no. r rev. 32v , 32-lead (8 x 14 mm package) plastic thin small o u tline package, type i ( v sop) b 32 v 10/18/01 pi n 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage pla n e seati n g pla n e l1 common dimensions (unit of meas u re = mm) symbol min nom max note n otes: 1. this package conforms to jedec reference mo-142, v ariation ba. 2. dimensions d1 and e do not incl u de mold protr u sion. allo w able protr u sion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maxim u m. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 13.80 14.00 14.20 d1 12.30 12.40 12.50 n ote 2 e 7.90 8.00 8.10 n ote 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
20 3499b?flash?4/06 at49bv040b 30. revision history revision no. history revisio n a ? sept. 2005 ? initial release revisio n b ? april 2006 ? combined the 3v and 5v part into one datasheet (bv). ? removed the speed of the part form the ordering information table. ? changed the address hold time to 20 ns.
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